Non-volatile Split Gate Memory Device And A Method Of Operating Same

ABSTRACT

A non-volatile memory device that a semiconductor substrate of a first conductivity type. An array of non-volatile memory cells is in the semiconductor substrate arranged in a plurality of rows and columns. Each memory cell comprises a first region on a surface of the semiconductor substrate of a second conductivity type, and a second region on the surface of the semiconductor substrate of the second conductivity type. A channel region is between the first region and the second region. A word line overlies a first portion of the channel region and is insulated therefrom, and adjacent to the first region and having little or no overlap with the first region. A floating gate overlies a second portion of the channel region, is adjacent to the first portion, and is insulated therefrom and is adjacent to the second region. A coupling gate overlies the floating gate. A bit line is connected to the first region. A negative charge pump circuit generates a first negative voltage. A control circuit receives a command signal and generates a plurality of control signals, in response thereto and applies the first negative voltage to the word line of the unselected memory cells. During the operations of program, read or erase, a negative voltage can be applied to the word lines of the unselected memory cells.

PRIORITY CLAIM

This application is a divisional of U.S. application Ser. No.14/506,433, filed on Oct. 3, 2014, and titled “Non-volatile Split GateMemory Device And A Method Of Operating Same,” which is incorporatedherein by reference.

TECHNICAL FIELD

The present invention relates to a non-volatile memory cell device and amethod of operating same. More particularly, the present inventionrelates to such memory device in which a negative voltage is applied tothe control gate and/or word line and selectively in combination withother terminals of the memory cells during the operations of read,program or erase.

BACKGROUND OF THE INVENTION

Non-volatile memory cells are well known in the art. One prior artnon-volatile split gate memory cell 10 is shown in FIG. 1. The memorycell 10 comprises a semiconductor substrate 12 of a first conductivitytype, such as P type. The substrate 12 has a surface on which there isformed a first region 14 (also known as the source line SL) of a secondconductivity type, such as N type. A second region 16 (also known as thedrain line) also of N type is formed on the surface of the substrate 12.Between the first region 14 and the second region 16 is a channel region18. A bit line BL 20 is connected to the second region 16. A word lineWL 22 is positioned above a first portion of the channel region 18 andis insulated therefrom. The word line 22 has little or no overlap withthe second region 16. A floating gate FG 24 is over another portion ofthe channel region 18. The floating gate 24 is insulated therefrom, andis adjacent to the word line 22. The floating gate 24 is also adjacentto the first region 14. A coupling gate CG (also known as control gate)26 is over the floating gate 24 and is insulated therefrom. A SL poly 28is connected to the first region 14 (source line SL).

In the prior art, various combinations of positive or zero voltages wereapplied to word line 22, coupling gate 26, and floating gate 24 toperform read, program, and erase operations. The prior art did not applynegative voltages for these operations.

One object of the present invention is the disclosure of a non-volatilememory cell device that applies a negative voltage to word line 22,coupling gate 26, and/or floating gate 24 during read, program, and/orerase operations.

SUMMARY OF THE INVENTION

The present invention relates to a non-volatile memory device that has asemiconductor substrate of a first conductivity type. An array ofnon-volatile memory cells is in the semiconductor substrate arranged ina plurality of rows and columns. Each memory cell comprises a firstregion on a surface of the semiconductor substrate of a secondconductivity type, and a second region on the surface of thesemiconductor substrate of the second conductivity type. A channelregion is between the first region and the second region. A word lineoverlies a first portion of the channel region and is insulatedtherefrom, and adjacent to the first region and having little or nooverlap with the first region. The wordline has a bottom arch region(region 27 in FIG. 1) that faces to a top tip corner of a floating gate(tip corner 25 in FIG. 1). The floating gate overlies a second portionof the channel region, is adjacent to the first portion, and isinsulated therefrom and is adjacent to the second region. A couplinggate overlies the floating gate. A bit line is connected to the firstregion. A negative charge pump circuit generates a first negativevoltage. A control circuit receives a command signal and generates aplurality of control signals, in response thereto and applies the firstnegative voltage to the word line of the unselected memory cells.

The present invention also relates to a method of operating anon-volatile memory cell device of the foregoing type.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view of a non-volatile memory cell of theprior art to which the method of the present invention can be applied.

FIG. 2 is a block diagram of a non-volatile memory device of the presentinvention using the non-volatile memory cell of the prior art shown inFIG. 1.

FIG. 3A and 3B are waveform diagrams of program/erase and readoperations, respectively, for use in the memory device of the presentinvention.

FIG. 4A and 4B are detailed circuit diagrams of a negative/positive wordline decoder circuit and negative charge pump, respectively, for use inthe memory device of the present invention.

FIG. 5A and 5B are detailed circuit diagram of a first negative/positivehigh voltage decoder circuit for use in the memory device of the presentinvention.

FIG. 6A and 6B are detailed circuit diagram of a secondnegative/positive high voltage decoder circuit for use in the memorydevice of the present invention.

FIG. 7A and 7B are detailed circuit diagram of a third negative/positivehigh voltage decoder circuit for use in the memory device of the presentinvention.

FIG. 8 is a detailed circuit diagram of a negative voltage charge pumpgenerator for use with the memory device of the present invention.

FIG. 9 is a detailed circuit diagram of a negative high voltageregulation circuit for use in the memory device of the presentinvention.

FIG. 10 is a detailed circuit diagram of a negative/positive pad circuitfor use in the memory device of the present invention.

FIG. 11A and 11B are cross sectional views showing a portion of aprocess flow of the prior art for use in making the memory device of theprior art.

FIG. 11C is a cross sectional view showing a portion of a process flowfor making the memory device of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Referring to FIG. 2 there is shown a block level diagram of anon-volatile memory device 50 of the present invention. In theembodiment shown in FIG. 2, the memory device 50 comprises two arrays52A and 52B of non-volatile memory cells 10 of the type shown in FIG. 1,arranged in a plurality of rows and columns in a semiconductor substrate12. Adjacent to each array 52 of non-volatile memory cells 10 is adecoder (Xdecoder 54A and 54B, respectively), for receiving addresssignals to be decoded and supplied to the word lines 22 of selected andunselected memory cells 10. Each of decoders 54 also has an associatenegative charge pump included in a charge pump 56 to generate a negativevoltage. A decoder (WSHDRHALFV, NCG) 80 placed in between the array 52Aand 52B provides voltage levels for the control gate 26 and thesourceline 14 as shown in embodiments in FIGS. 5-7.

Each of the memory arrays 52 of the memory device 50 also has aplurality of sensors 58 associated therewith to receive the signals fromthe memory cells 10 from the array 52 and to generate output signalsfrom the device 50. The memory device 50 also has a logic circuit 60.The logic circuit 60 receives commands such as program, erase or readissue by a host controller (not shown), external to the memory device 50to cause the memory device 50 to execute the various commands. Inresponse to the commands received, the logic circuit 50 generatescontrol signals that control the operation and the timing of the chargepump circuits 56 and the decoding circuits 54, and sense amplifiercircuits 58. The analog circuit 70 provides analog bias voltages andcurrents and timing for the device 50. A high voltage (positive,negative) control circuit 90 provides regulated and time-sequencedpositive and negative levels. A pad circuit 88 provides input buffers,IO buffers, Power pads (Vdd,Vss), Test pads, and ESD protection.

In response to the read, erase or program command, the logic circuit 60causes the various voltages to be supplied in a timely and least disturbmanner to the various portions of both the selected memory cell 10 andthe unselected memory cells 10.

For the selected and unselected memory cell 10, the voltage and currentapplied are as follows. As used hereinafter, the following abbreviationsare used: source line or first region 14 (SL), bit line 20 (BL), wordline 22 (WL), and coupling gate 26 (CG).

Operation #1: CG- unsel WL- BL- same CG- SL- WL unsel BL unsel CG sectorunsel SL unsel Read 1.0-3 V 0 V 0.6-2 V 0 V 0-2.6 V 0-2.6 V 0-2.6 V 0 V0 V Erase 11-10 V 0 V 0 V 0 V 0 V 0 V 0 V 0 V 0 V Program 1 V 0 V 1 uA Vinh 8-11 V 0-2.6 V 0-2.6 V 4.5-5 V 0-1 V

Operation #2: CG- unsel WL- BL- same CG- SL- WL unsel BL unsel CG sectorunsel SL unsel Read 1.0-2 V −0.5 V/0 V 0.6-2 V 0 V 0-2.6 V 0-2.6 V 0-2.6V 0 V 0 V Erase 11-10 V 0 V 0 V 0 V 0 V 0 V 0 V 0 V 0 V Program 1 V −0.5V/0 V 1 uA V inh 8-11 V 0-2.6 V 0-2.6 V 4.5-5 V 0-1 V

Operation #3: WL- BL- CG-unsel CG- SL- WL unsel BL unsel CG same sectorunsel SL unsel Read 1.0-2 V −0.5 V/0 V 0.6-2 V 0 V 0-2.6 V 0-2.6 V 0-2.6V 0 V 0 V Erase 9-6 V −0.5 V/0 V 0 V 0 V −(5-9) V 0 V/−(5-9) V 0V/−(5-9) V 0 V 0 V Program 1 V −0.5 V/0 V 1 uA V inh 8-9 V 0-2.6 V 0-2.6V 4.5-5 V 0-1 V

Operation for erase and program of non-volatile memory cell 10 is asfollows. The cell 10 is erased, through a Fowler-Nordheim tunnelingmechanism, by applying a high voltage on the word line 22 with otherterminals equal to zero volt or negative. Electrons tunnel from thefloating gate 24 into the word line 22 to be positively charged, turningon the cell 10 in a read condition. The tunneling is from the FG tip 25to the arch wrap around region 27 of the WL 22. The resulting cellerased state is known as ‘1’ state. The cell 10 is programmed, through asource side hot electron programming mechanism, by applying a highvoltage on the coupling gate 26, a high voltage on the source line 14,and a programming current on the bit line 20. A portion of electronsflowing across the gap between the word line 22 and the floating gate 24acquire enough energy to inject into the floating gate 24 causing thefloating gate 24 to be negatively charged, turning off the cell 10 inread condition. The resulting cell programmed state is known as ‘0’state. Read operation is done by applying a positive bias on the bitline20, a positive bias on the WL 22, zero volt on the source line 14, and apositive or a zero volt on the coupling gate 26. With this readcondition memory cell with state ‘1’ conducts a current and memory cellwith state ‘0’ conducts no or low current level. For un-selected WLszero or negative voltage can be applied for read and program condition.

In the erase operation #3, WL is at a positive HV, e.g., 9-6V, CG is ata negative HV, e.g., −(5-9)V. Un-selected WL can be at OV or at anegative voltage, e.g., −(0.5-5)V, un-selected CG can be at a 0V or at anegative HV, e.g., −(5-9)V (same as selected negative CG HV voltage).

Alternatively, the program operation can be performed with the Psubstrate Vsub 12 being negative instead of 0V, e.g., −6V.

Referring to FIG. 3A there is shown one example of a signal timingwaveform for program and erase signals for positive/negative bias levelsas described above for use in the memory device 50 of the presentinvention. Signals WL, BL, CG, SL as corresponding respectively toterminals WL, BL, CG, SL of the memory cell 10 are as described above.For programming, a signal WL 102 goes to high (e.g., ˜Vdd) first (suchas to set control signal in the decoder circuit 80 to be describedlater) then start to settle down (to a bias voltage Vpwl). Then signalBL 104 and CG 106 goes high, e.g., ˜Vinh=˜Vdd and 10 to 11 vrespectively, and then SL 110 goes high (e.g., ˜4.5 v to 5 v).Alternatively CG 106 goes high after SL 110 (as shown by the dotted linewaveform). The signal WL 102 settles down to a voltage Vpwl, e.g., 1 v,and the signal BL 104 settles down to a voltage Vdp, e.g., ˜0.5 v as CGgoes high. Unselected WLs goes down to 0 v or negative, e.g., −0.5 v,before or concurrent with selected WL 102 goes high. Unselected CGsstays at value in standby, e.g., 0 to 2.6 v. Unselected SLs stays at avalue in standby, e.g., 0 v or switches to a bias voltage, e.g., 1 v, asCG 106 goes high (unselected SL switching to a bias level to preventleakage current through unselected cells through the BLs).

The signal BL 104 goes first high to Vinh (inhibit voltage) to preventinadvertent program disturb due various signals are not settled yetduring ramping to programming voltages. The timed sequence CG 106 vs. SL110 are optimized to reduce disturb effect, e.g. whichever signal causesmore disturb goes high last. The ramping down of programming pulses arereversed in order to minimize disturb (i.e., signal that goes up firstnow goes down last). The signal SL 110 goes down, then CG 106 goes down,then WL 102 and BL 104 goes down. In the embodiment of programming withthe substrate P going negative, e.g., −1V, this negative switching isconcurrent with the signal WL goes low or the CG goes high.

For erase, the signal WL 102 goes high, e.g., Vdd, (such as to setcontrol signal in the decoder circuit 80 to be described later asembodiments in FIGS. 5-7) then goes low, e.g., 0V (or alternatively anegative such as −0.5V). At approximately same time or a short timethereafter as the WL 102 going low, the signal CG 106 goes negative,e.g., −6V to −9V. The selected WL 102 then goes high, e.g., 9V to 6V.The signals BL 104, SL 110 stays at a value in standby, e.g., 0V.Unselected WLs goes down to 0V or negative, e.g., −0.5V, before orconcurrent with selected WL 102 going high. Unselected CGs stay at valuein standby, e.g., 0 to 2.6V. Unselected SLs stay at a value in standby,e.g., 0V.

In the another embodiment of erase ,the substrate P going negative,e.g., −6V.

The ramping down of erase pulses is approximately reversed in order(i.e., signal that goes up first now goes down last). The signals WL 102and CG 106 goes to standby value, e.g., 0V.

Referring to FIG. 3B there is shown one example of a signal timingwaveform for read signals for positive/negative bias levels as describedabove for use in the memory device 50 of the present invention. Thisread signal waveform goes with the program and erase signal waveform inFIG. 3A for complete non-volatile erase/program/read operation. For ReadNormal waveform, the SL 110 is at standby value, e.g., 0V. The CG 106 isat standby value, e.g., 0V or 2.6V, or alternatively switching to a biasvalue in read, e.g. 2.6V (to help increase the memory cell current dueto CG voltage coupling to FG potential in read condition). The standbyvalues are similar to those for program and erase condition. The WL 102and BL 104 switch to bias level in read, e.g. 2.6V and 1.0V respectivelyto selected memory cells for reading.

A Read Margin( ) operation is performed after programming the wholearray to detect weak programming cells. After programming, the cellcurrent is at a very low value normally <nano amperes (nA), thiscorresponds to reading out a ‘0’ digital value (no cell current).However some cells may marginally stay at a couple micro amperes (due toweak programming due to various reasons such as cell leakage, weak cellprogramming coupling ratio, process geometrical effect, etc. . . . ) andthis can causing read ‘0’ to fail during the operating lifetime of thememory device 50. A Read Margin( ) is used to screen out those weakcells. For Read Margin( ) waveform, the SL 110 is at standby value,e.g., 0 v. The WL 102 and BL 104 switch to bias level in read, e.g. 2.6v and 1.0 v respectively to selected memory cells for reading as in ReadNormal condition. The CG 106 is biased at a margin( ) value (provided bysame circuit means described in FIGS. 6-8 as for program or readcondition) in read, e.g. 3 v, to detect weak programmed cells. The CGvoltage will couple into FG potential to amplify the weak programmingeffect, effectively increase the cell current, so the weak cells nowread as a ‘1’ instead of a ‘0’ (effectively there is cell currentinstead of no cell current).

A Read Margin1 operation is performed after erasing the whole array todetect weak erased cells. Negative CG now (provided by same circuitmeans described in FIGS. 6-8 as for erasing with negative voltage) isutilized to detect this condition. The SL 110 is at standby value, e.g.,0 v. The WL 102 and BL 104 switch to bias level in read, e.g. 2.6 v and1.0 v respectively to selected memory cells for reading as in ReadNormal condition. The CG 106 is biased at a margin1 value in read, e.g.−3 v, to detect weak erased cells. The CG voltage will couple negativelyinto FG potential to amplify the weak erased effect, effectivelydecrease the cell current (less FG potential), so the weak erased cellsnow read as a ‘0’ instead of a ‘1’ (effectively there is no cell currentinstead of cell current).

Referring to FIG. 4A there is shown one example of a circuit diagram ofthe Xdecoder 200 for use in the memory device 50 of the presentinvention. The Xdecoder circuit 200 provides the decoded address signalsto be supplied to the word lines 22 of the selected and unselectedmemory cells 10. The Xdecoder circuit 200 operates in the followingmanner. NAND gate 201 and INV 202 is used for decoding wordline (row)pre-decoded signal XPA-XPC (which is called memory sector (address)selection). Circuit 280 consists of a pre-driver and a (wordline)driver. PMOS transistors 210 and 211 and NMOS transistor 212 arewordline pre-driver combined with pre-decoded XPZ<0:7>. Pre-decodedsignals XPZ<0:7) is used to select one row out of eight (by being=‘0’).PMOS transistor 213 and NMOS transistor 214 are wordline WL driver, usedto drive a memory row that includes typically 2048 or 4096 cells in arow and hence needing big size transistor for wordline RC delay, i.e.,large W/L ratio, W=transistor width and L=transistor length. The circuit280 is repeated 8 times and NAND 201 and INV 202 is repeated one timefor 8 rows per memory sector size. Typically the source of thetransistor 214 is connected to a ground node (i.e., 0 v) forde-selection condition, here it is connected to a node NWLLOW 240. Thesource of the transistor 213 is connected to a node ZVDD 220, which isequal to Vwlrd (read wordline voltage) in read operation, equal to Vpwl(programming wordline voltage in programming operation). For programmingcondition, for selected wordline, WL=ZVDD=Vpwl=1.0 v for example, forunselected WLs=NWLLOW, which is equal to −0.5 v. For erase condition,for selected wordline WL and un-selected WLS=NWLLOW=-0.5 vin oneembodiment. For read condition, for selected wordline, WL=ZVDD=Vwlrd=2 vfor example, for un-selected wordlines WLS=NWLLOW, which is equal to−0.5 v in one embodiment. Wordline deselect lines 250 can be used todeselect specific word lines during programming. NMOS native highvoltage (HV) transistor 290-297 serves as isolation transistor toisolate erase high voltage on voltage on low voltage transistors 213 and214, They also serves as pass gate in read and program operation. WLISOline 299 is control bias for gate of transistors 290-267, going low,e.g., 1 v, during erase and high, e.g., 3-5 v. during read and program.

Referring to FIG. 4B there is shown one example of a circuit diagram ofa negative charge pump generator 260 (which is part of the charge pump56 that provides both negative and positive voltages) for generating anegative voltage to be supplied to the word lines 22. The negativecharge pump circuit 260 operates in the following manner. In a firsttime period, PMOS transistor 263 and NMOS transistor 266 are used tocharge (+) 268 and (−) terminal 269 of a capacitor 265 to a positivebias voltage NBIAS 267 and a ground level (i.e., 0 v) respectively. In anext time period after the first period, the transistor 266 is turnedoff and a NMOS transistor 264 is turned on to discharge the (+) terminal268 of the capacitor 265 from a bias level 268 to ground level. At thistime, the (−) terminal 269 of the capacitor 265 will be capacitivelycoupled to a negative level, e.g., −0.5 v, depending on value of thecapacitor 265 to the capacitive loading at the node NWLLOW 240. Byadjusting level of NBIAS 267 and the value of the capacitor 265, thenegative level is adjusted. For the embodiment of a semiconductorprocess using P substrate=0 v (grounded) for forming the memory device50, e.g., single well CMOS (P-substrate for N type devices and a singleN well for P type devices), the negative level is clamped at a P/N+forward junction forward bias (˜−0.6 v). As is well known, the memorydevice 50 can be made of a twin well P-sub CMOS process, in which twowells (P well and N well) are constructed in the substrate 12. Since thesubstrate 12 is of P type conductivity, a first P well therein would befor N type devices (NMOS), and a second N type well would be for P typedevices (PMOS). The negative voltage charge pump generator 260 and thewordline decoder 200 can be made in a triple well in the substrate 12.This is done by a triple well CMOS process instead of the twin wellP-sub CMOS process described earlier. In that event, the negative pumpgenerator 260 and the wordline decoder 200 would be made in a third Ptype well (which is made in the second N type well, which is inside thesubstrate 12) and the second N type well. This third P type well can nowbe applied negative voltage which is advantageous in certain operatingconditions. Although constructing the memory device 50 having a triplewell is more process intensive, the benefit of having the pump generator260 and the wordline decoder 200 in a triple well is that the negativevoltage applied to the word line 22 can be more negative, for example−6.0 v used for an erase embodiment, (i.e. not clamped by the P/N+junction forward bias ˜−0.6 v). In this case the third P type wellvoltage condition can be negative to avoid the P/N+ junction forwardbias, e.g., −6.0 v or −8.0 v or −5.6 v. In an embodiment the memory cell10 can be formed in the third P type well.

Referring to FIG. 5 there is shown a first embodiment of a high voltagedecoding circuit 300 for positive/negative level signals for use in thememory device 50 of Psub CMOS process of the present invention. Acircuit 320 consisting of hv (high voltage, e.g. 12 v) PMOS transistors321 and 322 and hv NMOS transistor 323 and 1 v (low voltage, e.g., 3 v)transistors 324 and 325 are used for decoding WL signal forerase/program/read operation. The transistor 322 WL current limiter isused to limit current in erase and/or program (to limit current sinkingfrom the HV charge pump). A circuit 310 is a hv latch circuit used toenable the hv control for the sector (1 sector per 8 rows) selected,which is selected once a WL signal is asserted (˜Vdd) at the beginningof the erase or programming sequence as shown in FIG. 3A. A circuit 350consisting of native hv NMOS transistor 351, inverter 352, NAND 353, alv latch (consisting of inverter 354 and 355 and set 1 v NMOStransistors 356, 359, 358 and reset lv NMOS transistor 357) is used todisable the hv signal if the sector is bad sector (not to be used). Acircuit 330 consisting of 1 v PMOS transistors 331 and 332 and hv PMOStransistor 333 is used to provide CG bias level in standby and read. Thetransistor 331 (its gate is at a bias level) acts as current limiter toCG terminal to limit current from bad CG terminal such as in standbycondition. A circuit 340 consisting of hv PMOS transistors 341 and 342is used to provide CG bias level in erase/program. The transistor 341could act as current limiter to CG terminal in erase/program to limitcurrent supplied from HV chargepump. A circuit 360 consisting of hv PMOStransistor 361, hv native NMOS transistor 362, lv NMOS transistors 363and 364 is used to disable the CG. A circuit 370 consisting of hv PMOStransistor 371, hv NMOS transistor 373 and lv NMOS transistor 372 isused to enable SL signal for erase/program/read condition. The 1 v NMOStransistor 372 is used to pulldown the SL to ground in read and eraseand to a bias level, e.g. <2 v, in program. A circuit 380 is a negativedecoding circuit for the CG signal. The circuit 360 uses PMOS transistor361 as isolation transistor to isolate negative level (provided by thecircuit 380 going into CG terminal of memory cell) from the NMOStransistor 362 for Psub CMOS process. The circuit 380 uses clockednegatively bootstrapped high voltage circuit scheme. The circuits 380consists of PMOS transistors 381, 382, 385-391 and NOR 384 and inverter384. The NOR 384 and inverter 384 is used to enable a clocking signalinto the PMOS transistors 386 and 388 which act as a capacitor tonegatively pumping gate of the transistor 387. The transistor 385 actsas a bootstrap transistor for the PMOS transistor 387 and the PMOScapacitors 386 and 388. The transistors 381/390 and 382/391 serves toclamp the drain of the transistor 387 and the drain of the transistor385 respectively at Vdd level. The transistor 389 serves as a buffer fornegative level into CG. The sources of transistors 385 and 387 connectto a negative power supply VCGNEG 399.

Referring to FIG. 6 there is shown second embodiment of a high voltagedecoding circuit 400 for positive/negative level signals for use in thememory device 50 of Triple well CMOS process of the present invention.The circuits 310-350, 370 are same or similar as those of FIG. 5. Acircuit 410 consisting of hv NMOS transistor 410 and lv NMOS transistors412-414 is used for de-selecting the CGs to a low level, e.g., 0 v. Thehv transistor 410 serves as isolation transistor to isolate the negativelevel into CGs, hence its bulk VCGNEG also at a negative level. Acircuit 420, serves as a negative level shifter, is used to providenegative level for CGs. The circuit 420 consists of NAND 421, inverter422 as enabling entity and hv PMOS transistors 423 and 424 and hv NMOStransistors 425 and 426 as a cross-coupled negative latch and hv NMOStransistor 427 as a buffer. The sources of NMOS transistors 425, 426,427 connect to a negative power supply VCGNEG.

Referring to FIG. 7 there is shown third embodiment of a high voltagedecoding circuit 420 for positive/negative level signals for use in thememory device 50 of Psub CMOS process of the present invention. It useda diode decoding scheme for negative voltage. The circuits 310-370 aresame or similar as those of FIG. 5. A circuit 510 consisting of hv PMOStransistor 512 is used to provide negative level into CGs. Thetransistor 512 is diode-connected, meaning gate-drain connectedtogether, and its gate-drain is connected to a negative power supplyVCGNEG. Its source is connected to CG. Hence as the negative powersupply VCGNEG goes negative, the source of the transistor goes negativeby an amount=VCG NEG-IVtpl.

Referring to FIG. 8 there is shown a negative charge pump 600 thatgenerates the negative voltages that are applied to the coupling gate 26during the erase operation. A circuit 610 consists of PMOS transistors612 and 613 and capacitors 611 and 614 constitutes a pump stage. Thetransistor 613 is the transfer transistor (transferring charge from onestage to next stage). The transistor 612 and the capacitor 611 serves asVt-cancelling function for the transferring transistor 613. Thecapacitor 614 is the pump capacitor (meaning provide pumping charge). Adiode-connected PMOS transistor 620 connects to a power supply node tofirst pump stage. A diode connected PMOS transistor 640 serves toconnect to an output charge pump node from last pump stage. PMOStransistors 650 and 652 serve to clamp or initialize internal pumpednodes. Various clock generation, phase driver, and biases are not shown.

Referring to FIG. 9 there is shown an embodiment of a negative highvoltage regulation circuit 700 for use in the memory device 50 of thepresent invention. Capacitors 702 and 704 are used to divide thenegative voltage from the negative power supply VCGNEG 399 into avoltage to be compared with a reference voltage VREF 708, e.g. 1 v. TheVREF 708 is coupled to a terminal of a comparator 710. A transistor 714is used to initialize node 706 to a bias voltage, e.g., 2 v. The node706 is coupled to other terminal of the comparator 710. As the negativesupply VCGNEG 399 is pumped negative progressively from a level such asground, the node 706 proportionally goes from a bias level , e.g.positive 2 v, to progressively lower in a negative direction (by theratio determined by values of the capacitors 702 and 704). Once the node706 reaches a value equal to VREF 708, the comparator 710 switchespolarity. The output REGOUT 718 is then used to signal that the negativepower supply VCGNMEG 399 has reached a desired level such as −9 v usedfor CG in erase condition.

Referring to FIG. 10 there is shown an embodiment of a negative test padcircuit 800 for use in the memory device 50 in Psub CMOS process of thepresent invention. PMOS transistor 810 serves to isolate NMOS transistor812 to a negative level to be transferred from internal to external pador vice versa. The transistor 810 has its bulk connected to its drainfor the purpose of isolation. The transistor 812 serves as ESD clamping.

Referring to FIGS. 11A and 11B there are shown prior art embodiments ofa process flow cross section 900 and 901 to produce memory cells havingpositive high voltage operation of the prior art. A memory cell includeslayer 904 (CG poly), 905 (ONO), 906 (FG poly), 908 (SL poly) 912 (SLdiffusion layer), 914 (FG gate oxide), 955 (WL poly). For process flowcross section 900, peripheral HV device includes 982 (gate poly), 988(channel region underneath the gate poly), LDD 980 (LDD implant). Forthis case the peripheral HV gate poly 982 is thick which can stop theLDD implant 980 from going into the channel region 988. For process flowcross section 901, which is applicable to advanced smaller geometrytechnology node, the memory cell includes WL poly 965 , and peripheralHV device includes 984 (gate poly), 988 (substrate), LDD 980 (LDDimplant). The gate poly 984 is significantly thinner than that of thegate poly 982. In this case LDD implant 980 penetrates gate poly 984into the channel region 988 which modulate the channel 988 electrically.This effect is undesirable. In this case additional masking and/orprocess layer step may be needed to stop LDD implant from penetratinginto the channel.

Referring to FIG. 11C there is shown an embodiments of a process flowfor the production of memory cells 10 having negative voltage operationfor use in the memory device 50 in the present invention. LDD implant981 in this case is significantly lower energy due to the lower highvoltage requirement, e.g. 9 v vs. 11 v for negative voltage operation.Hence in this case even with smaller geometry technology node, with thingate poly 984 thickness, LDD implant does not penetrate into the channel988. This process flow hence is suitable for producing memory cell foruse with negative voltage operation.

The benefits of applying a negative voltage to the word line 22 of theunselected or selected memory cells 10 during the operations of read,erase and program are to allow the memory cell to be scaled down moreeffectively. During erase, negative voltage on wordline of selectedmemory cells allows overall erase voltage to be lowered thus allowingcell dimension to be smaller (sustaining less voltage across variousinter-cell or inter-layer dimensional horizontal or vertical spacing,isolation, width, length, etc. . . . ). During program, negative voltageon wordline of unselected memory cells reduces leakage for un-selectedmemory cells leading to less disturb (for un-selected cells in samesector), more accurate programming current (for selected cells, lessleakage interference) and less power consumption. For read, negativevoltage on wordline of unselected memory cells leads to more accuratesensing due to less interference from leakage. It is also advantageousto combine negative wordline, negative coupling gate and negative Psubstrate for use in memory array operation resulting in lowerederase/program voltages and current, more effective erasing andprogramming, less cell disturb, and less cell leakage.

What is claimed is:
 1. A non-volatile memory device comprising: asemiconductor substrate of a first conductivity type; an array ofnon-volatile memory cells in the semiconductor substrate arranged in aplurality of rows and columns, each memory cell comprising: a firstregion on a surface of the semiconductor substrate of a secondconductivity type; a second region on the surface of the semiconductorsubstrate of the second conductivity type; a channel region between thefirst region and the second region; a word line overlying a firstportion of the channel region and insulated therefrom, and adjacent tothe first region and having little or no overlap with the first region;a floating gate overlying a second portion of the channel region,adjacent to the first portion, and insulated therefrom and adjacent tothe second region; a coupling gate overlying the floating gate; a bitline connected to the first region; a negative charge pump circuit forgenerating a first negative voltage; and a control circuit for receivinga command signal and for generating a plurality of control signals tocontrol the application of the first negative voltage to the couplinggate of the selected memory cells, in response thereto, wherein saidcontrol circuit comprises a current limiter in the high voltage decoderfor supplying positive or negative high voltages to said memory cells.2. A non-volatile memory device comprising: a semiconductor substrate ofa first conductivity type; an array of non-volatile memory cells in thesemiconductor substrate arranged in a plurality of rows and columns,each memory cell comprising: a first region on a surface of thesemiconductor substrate of a second conductivity type; a second regionon the surface of the semiconductor substrate of the second conductivitytype; a channel region between the first region and the second region; aword line overlying a first portion of the channel region and insulatedtherefrom, and adjacent to the first region and having little or nooverlap with the first region; a floating gate overlying a secondportion of the channel region, adjacent to the first portion, andinsulated therefrom and adjacent to the second region; a coupling gateoverlying the floating gate; a bit line connected to the first region; anegative charge pump circuit for generating a first negative voltage;and a control circuit for receiving a command signal and for generatinga plurality of control signals to control the application of the firstnegative voltage to the coupling gate of the selected memory cells, inresponse thereto, wherein said control circuit comprises a currentlimiter in a high voltage decoder for supplying an erase voltage on theword line to said memory cells.
 3. A non-volatile memory devicecomprising: a semiconductor substrate of a first conductivity type; anarray of non-volatile memory cells in the semiconductor substratearranged in a plurality of rows and columns, each memory cellcomprising: a first region on a surface of the semiconductor substrateof a second conductivity type; a second region on the surface of thesemiconductor substrate of the second conductivity type; a channelregion between the first region and the second region; a word lineoverlying a first portion of the channel region and insulated therefrom,and adjacent to the first region and having little or no overlap withthe first region; a floating gate overlying a second portion of thechannel region, adjacent to the first portion, and insulated therefromand adjacent to the second region; a coupling gate overlying thefloating gate; a bit line connected to the first region; a negativecharge pump circuit for generating a first negative voltage; and acontrol circuit for receiving a command signal and for generating aplurality of control signals to control the application of the firstnegative voltage to the coupling gate of the selected memory cells, inresponse thereto, wherein said control circuit comprises a currentlimiter in a high voltage decoder for supplying a voltage on thecoupling gate of said memory cells.
 4. The non-volatile memory device ofclaim 3 wherein said control circuit comprises a current limiter in ahigh voltage decoder for supplying a voltage on the coupling gate ofsaid memory cells during program or erase operations.
 5. A non-volatilememory device comprising: a semiconductor substrate of a firstconductivity type; an array of non-volatile memory cells in thesemiconductor substrate arranged in a plurality of rows and columns,each memory cell comprising: a first region on a surface of thesemiconductor substrate of a second conductivity type; a second regionon the surface of the semiconductor substrate of the second conductivitytype; a channel region between the first region and the second region; aword line overlying a first portion of the channel region and insulatedtherefrom, and adjacent to the first region and having little or nooverlap with the first region; a floating gate overlying a secondportion of the channel region, adjacent to the first portion, andinsulated therefrom and adjacent to the second region; a coupling gateoverlying the floating gate; a bit line connected to the first region; anegative charge pump circuit for generating a first negative voltage;and a control circuit for receiving a command signal and for generatinga plurality of control signals to control the application of the firstnegative voltage to the coupling gate of the selected memory cells, inresponse thereto, wherein said control circuit comprises a high voltagelatch in a high voltage decoder for supplying voltages to said memorycells in program or erase or read operations.
 6. A non-volatile memorydevice comprising: a semiconductor substrate of a first conductivitytype; an array of non-volatile memory cells in the semiconductorsubstrate arranged in a plurality of rows and columns, each memory cellcomprising: a first region on a surface of the semiconductor substrateof a second conductivity type; a second region on the surface of thesemiconductor substrate of the second conductivity type; a channelregion between the first region and the second region; a word lineoverlying a first portion of the channel region and insulated therefrom,and adjacent to the first region and having little or no overlap withthe first region; a floating gate overlying a second portion of thechannel region, adjacent to the first portion, and insulated therefromand adjacent to the second region; a coupling gate overlying thefloating gate; a bit line connected to the first region; a negativecharge pump circuit for generating a first negative voltage; and acontrol circuit for receiving a command signal and for generating aplurality of control signals to control the application of the firstnegative voltage to the coupling gate of the selected memory cells, inresponse thereto, wherein said control circuit comprises a high voltagelevel shifter in a high voltage decoder for supplying voltages to saidmemory cells in program or erase or read operations.
 7. A non-volatilememory device comprising: a semiconductor substrate of a firstconductivity type; an array of non-volatile memory cells in thesemiconductor substrate arranged in a plurality of rows and columns,each memory cell comprising: a first region on a surface of thesemiconductor substrate of a second conductivity type; a second regionon the surface of the semiconductor substrate of the second conductivitytype; a channel region between the first region and the second region; aword line overlying a first portion of the channel region and insulatedtherefrom, and adjacent to the first region and having little or nooverlap with the first region; a floating gate overlying a secondportion of the channel region, adjacent to the first portion, andinsulated therefrom and adjacent to the second region; a coupling gateoverlying the floating gate; a bit line connected to the first region; anegative charge pump circuit for generating a first negative voltage;and a control circuit for receiving a command signal and for generatinga plurality of control signals to control the application of the firstnegative voltage to the coupling gate of the selected memory cells, inresponse thereto, wherein said control circuit comprises a low voltagelatch in a high voltage decoder for supplying voltages to said memorycells in program or erase or read operations.
 8. A non-volatile memorydevice comprising: a semiconductor substrate of a first conductivitytype; an array of non-volatile memory cells in the semiconductorsubstrate arranged in a plurality of rows and columns, each memory cellcomprising: a first region on a surface of the semiconductor substrateof a second conductivity type; a second region on the surface of thesemiconductor substrate of the second conductivity type; a channelregion between the first region and the second region; a word lineoverlying a first portion of the channel region and insulated therefrom,and adjacent to the first region and having little or no overlap withthe first region; a floating gate overlying a second portion of thechannel region, adjacent to the first portion, and insulated therefromand adjacent to the second region; a coupling gate overlying thefloating gate; a bit line connected to the first region; a negativecharge pump circuit for generating a first negative voltage; a controlcircuit for receiving a command signal and for generating a plurality ofcontrol signals to control the application of the first negative voltageto the coupling gate of the selected memory cells, in response thereto;and a low voltage decoder for supplying voltages to said memory cells inprogram or erase or read operations.
 9. The non-volatile memory deviceof claim 8, wherein the low voltage decoder comprises an isolationtransistor in a wordline driver for supplying voltages to said memorycells in program, erase, or read operations.